Superset pinouts are used on packages that house different densities of complex programmable logic devices (CPLD). Transceiver devices (or the like) with varying number of channels have unique pinouts to accommodate the varying I/O requirements. However, increasing the number of pins increases power consumption. Larger numbers of channels also need additional die space. Furthermore, programmable logic devices (PLDs) and transceiver devices are typically mounted in separate packages to accommodate unique I/O packaging requirements for each device.
Devices with combined programmable logic and high-speed serial channels are increasingly appearing in the marketplace. However, defining unique pinouts for parts with different programmable density or different high-speed serial transmission bandwidth within a family of parts makes applicability difficult for users (i.e., migration between higher and lower density parts). For example, when a user desires to switch to a transceiver with a larger number of high-speed serial channels, the board layout for the transceiver chip needs to be changed. Such a change can include the footprint of the transceiver device, routing of the transceiver chip, and/or other affected routing on the board. Additionally, complex routing and timing issues between the devices will have to be resolved.